1. Technical Field:
The present invention relates to exception handling for data processing systems and more particularly relates to improvements in handling exceptions for performance monitoring or the like in data processing systems.
2. Description of the Related Art:
The PowerPC.TM. architecture is a high-performance reduced instruction set (RISC) processor which has been produced in various implementations, including the PowerPC 604.TM. which is described in "PowerPC 604.TM. RISC Microprocessor User's Manual" published in 1994 by IBM Microelectronics and Motorola, incorporated herein by reference.
The PowerPC.TM. "architecture" is a definition of the instruction set, registers, addressing modes, and the like, for this specific computer system, as described in detail in "The PowerPC.TM. Architecture: A Specification for a New Family of RISC Processors." The architecture is somewhat independent of the particular construction of the microprocessor chips or chips used to implement an instance of the architecture. For example, the PowerPC.TM. computer architecture has been constructed in various implementations as the PowerPC 601.TM., 602.TM., 603.TM., and 604.TM.. These implementations have been described in detail in published manuals.
The PowerPC (as well as other processor architectures) defines certain functions which are useful for performance and analysis tools. The definition of these functions may be at the exception level. For example, exceptions may be defined for performance monitor, trace, and instruction address breakpoint. These functions employ special purpose on-chip registers which are an optional part of the architecture definition, and may be present in some implementations (e.g., the 604) but not in others. Exceptions must of course be fielded by the kernel; however, the analysis tools for functions such as performance monitor, trace, and instruction address breakpoint are actually more application-level than kernel-level. That is to say, the functions are specialized for specific types of analysis which does not necessarily relate to the generalized requirements of the kernel. Additionally, some of the functions are architected to be implementation-dependent. That is, one version of the architecture may have different implementations of similar functions, or, the function may not be present on each application.
The type of architecture just described, i.e., optional, kernel-level, and implementation-dependent functions, presents a support problem for the kernel, because the functions are optional and implementation-dependent. Since the support is not general and is chip-dependent, a large number of special-purpose modules would have to be added to the kernel to accommodate all of the possibilities for executing the functions with various platforms.